1. Field of the Invention
This invention relates to an improved method and apparatus for transmitting digital data at high speeds via a parallel data bus, and more particularly, to a method and apparatus that provides a cost effective short-haul interface for a wide variety of data transfer applications while eliminating precise bus length and system clock rates as a critical or limiting factor in system design.
2. Cross Reference to Related Applications
The present United States patent application is related to the following co-pending United States patent applications incorporated herein by reference:
Application Ser. No. 08/262,087, filed Jun. 17, 1994, now U.S. Pat. No. 5,487,095, entitled "Digital Phase Locked Loop with Improved Edge Detector," and assigned to the assignee of this application.
Application Ser. No. 08/261,522, filed Jun. 17, 1994, entitled "Multiple Processor Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,561, filed Jun. 17, 1994, entitled "Enhanced Input-Output Element," and assigned to the assignee of this application.
Application Ser. No. 08/261,603, filed Jun. 17, 1994, entitled "Massively Parallel System," and assigned to the assignee of this application.
Application Ser. No. 08/261,523, filed Jun. 17, 1994, entitled "Attached Storage Media Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,641, filed Jun. 17, 1994, entitled "Shared Channel Subsystem," and assigned to the assignee of this application.